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The DRAM Cell
Ed

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28. སྤྱི་ཟླ་བརྒྱད་པ 2026FI

The DRAM Cell

Robert Dennard's cell, patented at IBM in 1968 from a 1966 idea, is the most-manufactured object in human history. More DRAM cells exist than grains of sand on most beaches, and each one is a transistor and a capacitor and nothing else. The idea is almost insultingly simple. To store a bit, put charge on a capacitor. To keep it private, put a switch in front of the capacitor and leave the switch open. To read or write, close the switch. One transistor, one capacitor. Compare it with what came before, in the two blueprints this one links back to: magnetic core memory needed a ferrite ring threaded by hand with three or four wires, and a mercury delay line needed a tube of mercury and a transducer at each end. Compare it with the alternative that arrived alongside it — static RAM, the sibling blueprint — which needs six transistors per bit. Dennard's cell is the smallest way anyone has found to store a bit in silicon, and smallest means cheapest, and cheapest is why it won. The price is in the word DYNAMIC. Nothing holds the charge on that capacitor. It leaks — through the access transistor which is never perfectly off, through the junction into the substrate, through the dielectric. A cell written as a 1 becomes an unreadable 0 in something between milliseconds and a second. So the memory must read every cell and write it back before the charge falls too far, continuously, forever. That is refresh, and it is not a design flaw bolted on afterwards. It is the direct and unavoidable consequence of storing information as charge on an isolated node, and every DRAM ever made has spent part of its life doing it instead of serving the processor. You will build a single cell from a discrete MOSFET and a capacitor, watch a stored bit die on a scope, measure its half-life, and then measure how much shorter that half-life gets when you warm it up.
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6 hours

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1

The cell, drawn

Two components. Look at the schematic and note what is NOT there: no feedback, no latch, no power connection to the storage node at all. Once the wordline goes low, that node is connected to nothing, and the only thing keeping the bit alive is the charge sitting on the capacitor's plates. That isolation is the whole design. It is why the cell is small, and it is why the bit dies. THE ACCESS TRANSISTOR is an ordinary n-channel MOSFET. Its gate is the wordline, shared by every cell in a row. Its drain goes to the bitline, shared by every cell in a column. Its source is the storage node. So a cell is addressed by raising one wordline and reading one bitline, and the array is a grid — which is the second reason DRAM is cheap: the wiring per cell is two wires shared with thousands of neighbours. THE CAPACITOR is the part that got hard. In a modern cell it holds around 25 femtofarads, and it has to hold that in a footprint of a few hundred square nanometres. A flat plate of that capacitance would be enormous, so the industry went vertical: trench capacitors etched down into the substrate with aspect ratios past 50:1, or stacked capacitors built up above it. Getting 25 fF into that area is genuinely one of the hardest things done in manufacturing, and it is why DRAM is made by a handful of companies. Your bench version will use a 100 pF capacitor, which is four thousand times larger. That makes the retention time convenient to measure rather than impossibly short, and the physics is unchanged.

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ལག་ཆས་དགོས་མཁོ:

Desktop ComputerDesktop Computer
Notebook and PencilNotebook and Pencil
2

Build it and watch a bit die

Two components on a breadboard, and one measurement that has to be done carefully or it measures your instrument instead of the cell. THE BUILD. A 2N7000 n-channel MOSFET. Gate to a pin you can drive — that is the wordline. Drain to another driven pin through 1 kilohm — that is the bitline. Source to one leg of a 100 pF ceramic capacitor, other leg to ground. The junction of source and capacitor is the storage node. THE PROBLEM WITH MEASURING IT, and this is the step people get wrong. A scope probe is 1 megohm or 10 megohms to ground. Put that on a node holding charge on 100 pF and the RC time constant is 100 microseconds or 1 millisecond — so the probe drains the cell far faster than leakage does, and you measure your probe. You must either use a 10x probe with 10 megohm input and accept that you are measuring probe plus cell, or buffer the node. Buffering is better: a JFET-input op-amp as a unity-gain follower has an input impedance in the gigohms and will not load the node measurably. Build the follower, connect its input to the storage node and its output to the scope. State plainly which you did, because the retention figure means nothing without it. NOW WRITE A BIT. Set the bitline pin high, pulse the wordline high for a few milliseconds, then bring the wordline low. The capacitor is charged and isolated. Set the bitline pin to input so it floats and cannot hold the node up through the transistor's leakage. WATCH IT ON THE SCOPE, DC coupled, slow timebase — 1 second per division to start. You will see the stored voltage decay: fast at first if your transistor leaks, then slower. Photograph the trace. MEASURE THE RETENTION TIME. Define a threshold, say 60 percent of the written voltage, below which the bit can no longer be read reliably as a 1. Time from the write to that crossing. That is your retention time and it is the number the whole architecture is built around. EXPECT VARIATION BETWEEN PARTS. Try five transistors. Retention will vary by a factor of several, because leakage is dominated by whichever imperfection happens to be worst in that device. Real DRAM has exactly this problem at a scale of billions: the refresh interval is set by the WORST cell on the chip, not the average, and a handful of unusually leaky cells force the entire array to be refreshed far more often than it needs. Chips ship with redundant rows specifically to replace them.

གོམ་པ་འདིའི་རྫས་རིགས:

N-Channel MOSFET (2N7000)N-Channel MOSFET (2N7000)10 དུམ་བུ།
Ceramic Capacitor KitCeramic Capacitor Kit1 ཚན་པ།
JFET Op-Amp (TL071)JFET Op-Amp (TL071)5 དུམ་བུ།
Resistor Kit (1/4W, E12 Series)Resistor Kit (1/4W, E12 Series)1 ཚན་པ།
BreadboardBreadboard1 དུམ་བུ།
Jumper Wire SetJumper Wire Set1 ཚན་པ།

ལག་ཆས་དགོས་མཁོ:

Oscilloscope (2-Channel, 100MHz)Oscilloscope (2-Channel, 100MHz)
Digital Multimeter (Lab Grade)Digital Multimeter (Lab Grade)
Bench Power Supply (30V/5A)Bench Power Supply (30V/5A)
StopwatchStopwatch
3

Log retention against temperature

A scope trace gives you one number. What you want is a distribution, and how it moves with temperature — because temperature is what actually sets the refresh interval in a real part. This sketch writes a 1 into the cell, then samples the storage node repeatedly until the bit is no longer readable, logging voltage against time as CSV. It repeats five times and reads a DS18B20 so every run is stamped with the cell temperature. ONE THING IN THE SKETCH IS WORTH READING CAREFULLY, because it is not a workaround, it is how real DRAM behaves. Reading the cell requires opening the access transistor, which connects the storage capacitor to the bitline and to the ADC input. Charge is shared, so the act of reading DISTURBS the bit. In a real DRAM this is worse than a disturbance — the read is destructive, and the sense amplifier must immediately write the value back into the cell it just read. That write-back is not an optimisation, it is a requirement, and it is why a DRAM read cycle is longer than you would expect from the array alone. Here the sketch simply re-writes and starts a new run. Note in your results that the sampled decay curve is slightly faster than the true leakage, because every sample takes a little charge. Sampling less often gives a truer curve and worse resolution, which is a real measurement trade rather than a defect. RUN IT AT TWO TEMPERATURES. Room temperature first, then warm the transistor with a hairdryer to 50 or 60 degrees and run again. Junction leakage roughly doubles every 8 to 10 degrees Celsius, so expect retention to fall by a factor of four or more over that range. That is why server DRAM refreshes twice as often above 85 degrees, and why memory in a hot rack costs more bandwidth to maintain than the same memory in a cool one.
dram_logger.inocpp
// DRAM cell retention logger - measures how long ONE bit survives, against temperature.
// Board: ESP32 DevKit v1.  Cell: one N-channel MOSFET + one small capacitor.
//
// WHAT THIS MEASURES AND WHY IT IS THE WHOLE POINT OF DRAM:
// a 1T1C cell stores a bit as charge on a capacitor. Nothing holds it there. Leakage through
// the access transistor and the junction drains it, so the bit has a HALF-LIFE - and the entire
// architecture of DRAM exists to read every cell and write it back before that half-life runs out.
//
// You are measuring the number that forces refresh to exist.
//
// WIRING
//   GPIO 25  ->  WRITE_PIN   -> through 1k -> cell node (drives the bit line)
//   GPIO 26  ->  WORDLINE    -> MOSFET gate (opens the access transistor)
//   GPIO 34  ->  SENSE       -> cell node, ADC1, HIGH IMPEDANCE
//   DS18B20 on GPIO 4 for temperature
//
// THE MEASUREMENT IS DESTRUCTIVE, exactly as it is in a real DRAM: reading the cell shares its
// charge with the ADC input and disturbs it. Real DRAM solves this by writing the bit back
// immediately after every read. Here we simply re-write and start again.

#include <OneWire.h>
#include <DallasTemperature.h>

#define WRITE_PIN     25
#define WORDLINE_PIN  26
#define SENSE_PIN     34
#define ONE_WIRE_PIN   4

#define VREF        3.30f
#define ADC_MAX     4095.0f
#define LOGIC_HIGH  0.60f     // fraction of Vref still counted as a stored '1'

OneWire oneWire(ONE_WIRE_PIN);
DallasTemperature sensors(&oneWire);

float readCellVolts() {
  // Read WITHOUT opening the wordline would read nothing - the cell is isolated.
  // So: open the access transistor, sample fast, close it again.
  digitalWrite(WORDLINE_PIN, HIGH);
  delayMicroseconds(50);
  uint32_t acc = 0;
  for (int i = 0; i < 8; i++) acc += analogRead(SENSE_PIN);
  digitalWrite(WORDLINE_PIN, LOW);
  return (acc / 8.0f) * (VREF / ADC_MAX);
}

void writeCell(bool bit) {
  pinMode(WRITE_PIN, OUTPUT);
  digitalWrite(WRITE_PIN, bit ? HIGH : LOW);
  digitalWrite(WORDLINE_PIN, HIGH);     // open access transistor
  delay(5);                              // let the capacitor charge
  digitalWrite(WORDLINE_PIN, LOW);      // close it - the charge is now trapped
  pinMode(WRITE_PIN, INPUT);            // float the bit line so it cannot hold the node up
}

void setup() {
  Serial.begin(115200);
  pinMode(WORDLINE_PIN, OUTPUT);
  digitalWrite(WORDLINE_PIN, LOW);
  pinMode(WRITE_PIN, INPUT);
  analogSetPinAttenuation(SENSE_PIN, ADC_11db);
  sensors.begin();

  Serial.println("# DRAM cell retention");
  Serial.println("run,temp_c,ms_since_write,cell_v,still_one");

  for (int run = 1; run <= 5; run++) {
    sensors.requestTemperatures();
    float t = sensors.getTempCByIndex(0);

    writeCell(true);
    unsigned long t0 = millis();
    float v = VREF;

    // sample until the stored '1' is no longer readable as a '1'
    while (v > LOGIC_HIGH * VREF) {
      v = readCellVolts();
      Serial.printf("%d,%.2f,%lu,%.4f,%d\n", run, t, millis() - t0, v,
                    v > LOGIC_HIGH * VREF ? 1 : 0);
      delay(25);
      if (millis() - t0 > 60000UL) break;      // give up after a minute
    }
    Serial.printf("# run %d: retention = %lu ms at %.1f C\n", run, millis() - t0, t);
    delay(1000);
  }

  Serial.println("# DONE - paste the CSV into the jupyter step and fit the decay");
  Serial.println("# Then WARM THE CELL with a hairdryer and run again. Leakage roughly");
  Serial.println("# doubles every 8-10 C, so retention roughly halves. That temperature");
  Serial.println("# dependence is why real DRAM refreshes far more often when hot.");
}

void loop() { }

གོམ་པ་འདིའི་རྫས་རིགས:

ESP32 Development BoardESP32 Development Board1 དུམ་བུ།
DS18B20 Temperature Sensor (Waterproof)DS18B20 Temperature Sensor (Waterproof)1 དུམ་བུ།
N-Channel MOSFET (2N7000)N-Channel MOSFET (2N7000)5 དུམ་བུ།
Ceramic Capacitor KitCeramic Capacitor Kit1 ཚན་པ།
BreadboardBreadboard1 དུམ་བུ།

ལག་ཆས་དགོས་མཁོ:

Soldering Station (Temperature-Controlled)Soldering Station (Temperature-Controlled)
Digital Multimeter (Lab Grade)Digital Multimeter (Lab Grade)
Desktop ComputerDesktop Computer
Thermometer (Lab)Thermometer (Lab)
4

Refresh — what it costs to keep the bits alive

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ལག་ཆས་དགོས་མཁོ:

Desktop ComputerDesktop Computer
Notebook and PencilNotebook and Pencil
5

What DRAM replaced

Before you leave this cell, look at what it displaced, because the comparison is the reason DRAM matters rather than merely works. Magnetic core memory is embedded below rather than referenced, because it is worth actually reading. Every bit is a ferrite ring with wires threaded through it BY HAND — through the 1960s, largely by women working with needles and magnifiers, at a cost per bit that no amount of process improvement was ever going to fix. Core is non-volatile, which DRAM is not, and it survived a total power loss, which is why Apollo flew it. Dennard's cell beat it on one axis only: it can be PRINTED. Photolithography defines a million cells in the same exposure as one, so the cost per bit falls with every process generation instead of tracking the price of skilled labour. That is the same argument the Noyce blueprint makes about interconnect, arriving in a different place. Printed beats placed, not because the printed thing is better, but because its cost does not scale with quantity. Core memory's non-volatility, incidentally, is a genuine advantage that took the industry fifty years to get back. The floating gate in the next-but-one blueprint is the answer, and it arrived in 1971 — one year after the Intel 1103 made DRAM commercial.

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Notebook and PencilNotebook and Pencil

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