Your chip_core as Standard Cells: 42 GF180MCU Gates, Proven Equal to the Verilog

// SPDX-License-Identifier: Apache-2.0
// Youblob silicon rung 4: the PWM dimmer's logic written by hand as GF180MCU standard cells
// (gf180mcu_fd_sc_mcu7t5v0), the way a synthesis tool writes it. 42 cells.
//
//   count  <= rst_n ? count + enable : 0          8 half adders, 8 AND2, 8 flip-flops
//   pwm    <= rst_n & enable & (count < duty)     8 inverters, 1 half adder + 7 full adders, 1 AND3, 1 flip-flop
//
// The comparator is a subtractor whose answer is thrown away: duty + ~count carries out of
// bit 7 exactly when duty > count, which is count < duty.
// The library's dffq has no reset pin, so the reset goes in front of D: an AND gate forces 0
// on the next clock edge while rst_n is low. That is a synchronous reset, as in the RTL.

`default_nettype none

module pwm_gates (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       enable,
    input  wire [7:0] duty,
    output wire       pwm
);
    wire [7:0] count;      // flip-flop outputs
    wire [8:0] c;          // incrementer carry chain
    wire [7:0] sum;        // count + enable
    wire [7:0] d_next;     // sum, forced to 0 in reset
    wire [7:0] ncount;     // ~count
    wire [8:0] k;          // comparator carry chain; k[8] = (count < duty)
    wire       pwm_d;

    assign c[0] = enable;  // a connection, not a gate

    genvar i;
    generate
        for (i = 0; i < 8; i = i + 1) begin : bit_
            // counter bit i
            gf180mcu_fd_sc_mcu7t5v0__addh_1 inc (.A(count[i]), .B(c[i]), .S(sum[i]), .CO(c[i+1]));
            gf180mcu_fd_sc_mcu7t5v0__and2_1 rst (.A1(sum[i]), .A2(rst_n), .Z(d_next[i]));
            gf180mcu_fd_sc_mcu7t5v0__dffq_1 ff  (.CLK(clk), .D(d_next[i]), .Q(count[i]));
            // comparator bit i
            gf180mcu_fd_sc_mcu7t5v0__inv_1  inv (.I(count[i]), .ZN(ncount[i]));
        end
    endgenerate

    // bit 0 has no carry in, so a half adder does; bits 1..7 are full adders. The sums are not used.
`ifdef MUTANT
    // one missing inversion, the kind of slip this test exists to catch
    gf180mcu_fd_sc_mcu7t5v0__addh_1 cmp0 (.A(duty[0]), .B(count[0]), .S(), .CO(k[1]));
`else
    gf180mcu_fd_sc_mcu7t5v0__addh_1 cmp0 (.A(duty[0]), .B(ncount[0]), .S(), .CO(k[1]));
`endif
    generate
        for (i = 1; i < 8; i = i + 1) begin : cmp_
            gf180mcu_fd_sc_mcu7t5v0__addf_1 fa (.A(duty[i]), .B(ncount[i]), .CI(k[i]), .S(), .CO(k[i+1]));
        end
    endgenerate
    assign k[0] = 1'b0;    // unused; bit 0 is a half adder

    gf180mcu_fd_sc_mcu7t5v0__and3_1 pwm_and (.A1(enable), .A2(k[8]), .A3(rst_n), .Z(pwm_d));
    gf180mcu_fd_sc_mcu7t5v0__dffq_1 pwm_ff  (.CLK(clk), .D(pwm_d), .Q(pwm));
endmodule

`default_nettype wire

// SPDX-License-Identifier: Apache-2.0
// Both versions of the core side by side, fed the same inputs: the RTL (chip_core) and the
// standard-cell netlist (chip_core_gates). The cocotb test compares their outputs every clock.
`default_nettype none
module tb_equiv #(parameter NUM_INPUT_PADS = 4, NUM_BIDIR_PADS = 38, NUM_ANALOG_PADS = 4) (
    input  wire clk,
    input  wire rst_n,
    input  wire [NUM_INPUT_PADS-1:0] input_in,
    input  wire [NUM_BIDIR_PADS-1:0] bidir_in,
    output wire [NUM_BIDIR_PADS-1:0] out_rtl,
    output wire [NUM_BIDIR_PADS-1:0] out_gates
);
    wire [NUM_INPUT_PADS-1:0] ipu_r, ipd_r, ipu_g, ipd_g;
    wire [NUM_BIDIR_PADS-1:0] oe_r, cs_r, sl_r, ie_r, pu_r, pd_r, oe_g, cs_g, sl_g, ie_g, pu_g, pd_g;
    wire [NUM_ANALOG_PADS-1:0] analog;

    chip_core #(NUM_INPUT_PADS, NUM_BIDIR_PADS, NUM_ANALOG_PADS) rtl (
        .clk(clk), .rst_n(rst_n), .input_in(input_in), .input_pu(ipu_r), .input_pd(ipd_r),
        .bidir_in(bidir_in), .bidir_out(out_rtl), .bidir_oe(oe_r), .bidir_cs(cs_r), .bidir_sl(sl_r),
        .bidir_ie(ie_r), .bidir_pu(pu_r), .bidir_pd(pd_r), .analog(analog));

    chip_core_gates #(NUM_INPUT_PADS, NUM_BIDIR_PADS, NUM_ANALOG_PADS) gates (
        .clk(clk), .rst_n(rst_n), .input_in(input_in), .input_pu(ipu_g), .input_pd(ipd_g),
        .bidir_in(bidir_in), .bidir_out(out_gates), .bidir_oe(oe_g), .bidir_cs(cs_g), .bidir_sl(sl_g),
        .bidir_ie(ie_g), .bidir_pu(pu_g), .bidir_pd(pd_g), .analog(analog));
endmodule
`default_nettype wire

# SPDX-License-Identifier: Apache-2.0
# Gate-level check for the PWM dimmer: the hand-written GF180MCU cell netlist against the RTL,
# simulated with the PDK's own functional cell models (gf180mcuD, the commit the template pins).
import os
import random
from pathlib import Path

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import ClockCycles, FallingEdge, RisingEdge
from cocotb_tools.runner import get_runner

PWM_PAD = 8
PDK = Path(os.getenv("PDK_ROOT", "pdk")) / "gf180mcuD" / "libs.ref" / "gf180mcu_fd_sc_mcu7t5v0" / "verilog"


async def start(dut):
    cocotb.start_soon(Clock(dut.clk, 20, unit="ns").start())
    dut.input_in.value = 0
    dut.bidir_in.value = 0
    dut.rst_n.value = 0
    await ClockCycles(dut.clk, 2)
    dut.rst_n.value = 1


@cocotb.test()
async def test_reset_clears_x(dut):
    """Before the first clock the flip-flops hold X; one clock with reset low makes them 0."""
    cocotb.start_soon(Clock(dut.clk, 20, unit="ns").start())
    dut.input_in.value = 1
    dut.bidir_in.value = 100
    dut.rst_n.value = 0
    await FallingEdge(dut.clk)                              # before any rising edge
    assert not dut.out_gates.value.is_resolvable, "flip-flops should start unknown"
    await RisingEdge(dut.clk)
    await FallingEdge(dut.clk)
    assert dut.out_gates.value.is_resolvable and int(dut.out_gates.value) == 0


@cocotb.test()
async def test_every_duty_lockstep(dut):
    """All 256 duty values, 300 clocks each: the gates and the RTL agree on every clock."""
    await start(dut)
    dut.input_in.value = 1
    checked = 0
    for duty in range(256):
        dut.bidir_in.value = duty
        for _ in range(300):
            await FallingEdge(dut.clk)
            assert dut.out_gates.value == dut.out_rtl.value, f"duty {duty}: gates {dut.out_gates.value} rtl {dut.out_rtl.value}"
            checked += 1
    dut._log.info(f"{checked} clocks compared, 0 differences")


@cocotb.test()
async def test_random_lockstep(dut):
    """Random duty changes, enable toggling and resets mid-run: still identical on every clock."""
    await start(dut)
    rng = random.Random(2026)
    for _ in range(20000):
        if rng.random() < 0.02:
            dut.bidir_in.value = rng.randrange(256)
        if rng.random() < 0.005:
            dut.input_in.value = rng.randrange(2)
        dut.rst_n.value = 0 if rng.random() < 0.001 else 1
        await FallingEdge(dut.clk)
        assert dut.out_gates.value == dut.out_rtl.value
    dut._log.info("20000 random clocks compared, 0 differences")


def test_runner():
    here = Path(__file__).resolve().parent
    defines = {"FUNCTIONAL": True}                          # the cells' logic only, no timing checks
    if os.getenv("MUTANT"):
        defines["MUTANT"] = True
    runner = get_runner("icarus")
    runner.build(
        sources=[PDK / "primitives.v", PDK / "gf180mcu_fd_sc_mcu7t5v0.v",
                 here / "pwm_gates.v", here / "chip_core.sv", here / "chip_core_gates.sv", here / "tb_equiv.sv"],
        hdl_toplevel="tb_equiv",
        defines=defines,
        build_args=["-g2012"],
        timescale=("1ns", "1ps"),
        always=True,
    )
    runner.test(hdl_toplevel="tb_equiv", test_module="test_equiv")


if __name__ == "__main__":
    test_runner()