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The Sense Amplifier
Penny

सिर्जनाकर्ता

Penny

28. अगस्ट 2026DK

The Sense Amplifier

The DRAM cell holds about 25 femtofarads of charge. The bit line it has to talk to is a wire running past thousands of other cells, and it carries 200 to 400 femtofarads of its own capacitance. When the access transistor opens, those two capacitances share their charge — and the cell, being ten to thirty times smaller, loses the argument almost completely. The result is that reading a DRAM cell produces a signal of roughly 50 to 100 millivolts on a line that swings a volt or more. The information is there, and it is buried in a fraction of the noise budget of everything around it. The sense amplifier is what recovers it, and the way it does so is one of the most elegant tricks in circuit design: it is the SAME cross-coupled latch as the SRAM cell in the previous blueprint, wired across the bit line pair, but used as an amplifier rather than as storage. Both bit lines are pre-charged to exactly half the supply and left floating. The cell tips one of them slightly. Then the latch is powered up — and a latch is a circuit with two stable states and an unstable point exactly between them, so a latch released from the unstable point falls towards whichever stable state the tiniest imbalance favours. The 50 millivolt difference decides which way it falls, and the latch's own positive feedback drives it the rest of the way to a full logic level. It is a coin balanced on its edge, tipped by a breath, and it lands decisively. Two consequences follow. Because the latch ends up driving the bit line hard to a full rail, and because the cell is still connected, the amplifier automatically WRITES THE BIT BACK — which is exactly what a destructive read requires, and it is free. And because a latch has no idea what it is amplifying, firing it before the signal has developed makes it decide on noise, confidently and wrongly. The timing of that fire signal is one of the tightest constraints in the whole part. You will build one from discrete parts, feed it a deliberately tiny difference, and find the smallest signal it can resolve.
उन्नत
5 hours

निर्देशनहरू

1

The latch, used as an amplifier

Compare this schematic with the SRAM cell in the previous blueprint. The four transistors in the middle are the same circuit — two inverters, cross-coupled. The difference is entirely in how it is used. In SRAM the latch is permanently powered and holds a bit. Here its supply rails are SWITCHED: SAP is pulled up and SAN pulled down only at the moment of sensing. Between reads the latch is unpowered and its nodes float at the pre-charge level. That is the whole trick. An unpowered latch sitting with both nodes at exactly VDD over 2 is at its unstable equilibrium point. It has two stable states either side and it is balanced precisely between them. Apply power and it must fall one way, and which way is decided by any asymmetry present at that instant — including a 50 millivolt difference put there by a memory cell. NOTE Cbl IN THE SCHEMATIC. That capacitor is not a component anybody fitted; it is the bit line's own parasitic capacitance, drawn because it dominates the problem. It is the wire's capacitance to the substrate and to its neighbours, accumulated over the length of the array, and it is ten to thirty times the cell it is trying to read. That ratio is the reason DRAM arrays are divided into sub-arrays with their own sense amplifiers. Making the bit line longer puts more cells on it, which is good for density, and adds capacitance, which shrinks the signal. Somewhere around 256 to 512 cells per bit line the signal gets too small to sense reliably, and that number — not the process — sets the sub-array size in every DRAM ever made. WHY BOTH BIT LINES. The amplifier is differential, and a reference is needed. In the folded bit line arrangement the pair runs side by side, so noise coupling from neighbouring lines lands on BOTH equally and cancels in the difference. The cell only ever tips one of them. That common-mode rejection is why the layout looks the way it does, and it is worth more than any amount of shielding.

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Desktop ComputerDesktop Computer
Notebook and PencilNotebook and Pencil
2

Build one and find the smallest signal it can resolve

Build the latch from discrete transistors rather than a logic IC, because you need access to the supply rails to switch them. THE LATCH. Two 2N7000 n-channel and two BS250 p-channel MOSFETs, or a CD4007 which gives you three complementary pairs in one package and is far easier. Cross-couple two inverters. Bring both supply rails out to switchable pins: SAP to a p-channel switch from VDD, SAN to an n-channel switch to ground. THE BIT LINES. Two 220 picofarad capacitors, one on each node, standing in for the bit line capacitance. Two more switches to pre-charge both nodes to VDD over 2 from a divider, and an equalising switch shorting the two nodes together — that equaliser matters, because it forces the two sides to start genuinely equal rather than merely nominally equal. THE SIGNAL. A third capacitor, 10 picofarads, standing in for the cell, charged separately to a level you set, and dumped onto one node through a switch. The ratio of 10 to 220 gives you roughly the same charge-sharing attenuation a real cell suffers. THE SEQUENCE, and the order is not negotiable: Equalise and pre-charge both nodes to VDD over 2, then open the pre-charge and equalise switches so both float. Dump the cell charge onto one node. Measure the difference on the scope — it should be tens of millivolts. Wait a defined delay. Fire SAP and SAN together. Watch the nodes separate to the rails. FIND THE SENSITIVITY. Reduce the cell voltage step by step and repeat, twenty times at each level, recording how often the amplifier lands on the correct side. Plot the error rate against the input difference. You will get an S-curve, not a threshold. Well above some level it is always right; well below it is a coin toss; and in between there is a band where it is right most of the time. That band is where offset and noise live, and its width tells you what your latch's own asymmetry is. NOW FIRE IT EARLY. Reduce the delay between the cell dump and the fire until the amplifier does not have time to see the full signal. The error rate climbs. Keep going and it approaches 50 percent — and notice that it never announces a problem. It produces a confident, full-swing, completely wrong answer. That silent confidence is why sense amplifier timing is designed with margin rather than optimised to the edge.

Materials for this step:

CD4007 CMOS Transistor ArrayCD4007 CMOS Transistor Array5 टुक्रा
N-Channel MOSFET (2N7000)N-Channel MOSFET (2N7000)10 टुक्रा
Ceramic Capacitor KitCeramic Capacitor Kit1 सेट
Resistor Kit (1/4W, E12 Series)Resistor Kit (1/4W, E12 Series)1 सेट
Logic IC Assortment (74HC Series)Logic IC Assortment (74HC Series)1 सेट
BreadboardBreadboard2 टुक्रा

Tools needed:

Oscilloscope (2-Channel, 100MHz)Oscilloscope (2-Channel, 100MHz)
Bench Power Supply (30V/5A)Bench Power Supply (30V/5A)
Digital Multimeter (Lab Grade)Digital Multimeter (Lab Grade)
ESP32 Development BoardESP32 Development Board
3

Sequence it and sweep the sensitivity

A sense amplifier is a timing device as much as a circuit, and neither of the measurements described in the previous step can be made by hand. The sequence needs microsecond resolution, and an error RATE needs hundreds of repetitions — do forty trials by hand and you have an anecdote. This sketch runs the full sequence — equalise, precharge, release, dump the cell charge, wait, fire — and sweeps it twice. SWEEP ONE varies the signal size at a generous development time, and gives you the sensitivity curve: how small a difference the latch can still resolve. SWEEP TWO holds the signal constant and varies the delay before firing, which is the timing margin. Both produce CSV. Paste it into the notebook in the next step and plot it. WHAT TO LOOK FOR, and it is stated in the sketch's closing comments because it is the lesson rather than the result: at every point in both sweeps the latch produces a clean, full-swing logic level. There is no intermediate output, no flag, no indication of low confidence. A sense amplifier fired too early is not slow or noisy — it is wrong, and it is wrong with exactly the same conviction as when it is right. Everything about DRAM timing margin follows from that.
sense_seq.inocpp
// Sense-amplifier sequencer and sensitivity sweep.
// Board: ESP32 DevKit v1. Drives the discrete latch built in step 2.
//
// The sense amplifier is a TIMING device as much as a circuit. Doing this by hand with
// switches cannot produce the microsecond-scale sequence it needs, and cannot repeat it
// the hundreds of times required to measure an error RATE rather than an anecdote.
//
// SEQUENCE, and the order is the whole thing:
//   1. EQ + PRECHARGE  - force both bit lines to exactly VDD/2, shorted together
//   2. release both    - the nodes now float at the unstable point of the latch
//   3. CELL dump       - share a small charge onto ONE node (this is the signal)
//   4. wait t_dev      - let the difference develop
//   5. FIRE SAP + SAN  - power the latch; it falls toward whichever side is higher
//   6. read the result, compare with what was written, count errors
//
// WIRING
//   GPIO 25  EQ         - shorts BL to BL_BAR (equalise)
//   GPIO 26  PRECHARGE  - connects both to VDD/2
//   GPIO 27  CELL       - dumps the cell capacitor onto BL
//   GPIO 14  CELL_SET   - charges the cell capacitor to the level under test
//   GPIO 12  FIRE       - drives SAP high and SAN low together
//   GPIO 34  READ_BL    - ADC1, reads BL after the latch has settled

#define EQ_PIN        25
#define PRECHARGE_PIN 26
#define CELL_PIN      27
#define CELL_SET_PIN  14
#define FIRE_PIN      12
#define READ_PIN      34

#define VREF     3.30f
#define ADC_MAX  4095.0f
#define TRIALS   40

void precharge() {
  digitalWrite(FIRE_PIN, LOW);          // latch unpowered - nodes may float
  digitalWrite(EQ_PIN, HIGH);           // short the pair together
  digitalWrite(PRECHARGE_PIN, HIGH);    // pull both to VDD/2
  delayMicroseconds(400);               // generous: the bit line caps are large
  digitalWrite(PRECHARGE_PIN, LOW);
  digitalWrite(EQ_PIN, LOW);            // both now FLOAT at the unstable point
  delayMicroseconds(20);
}

// dutyPct sets how hard the cell capacitor is charged, i.e. the signal size.
void chargeCell(int dutyPct) {
  ledcWrite(0, (dutyPct * 255) / 100);
  delayMicroseconds(300);
}

bool senseOnce(int dutyPct, int t_dev_us) {
  precharge();
  chargeCell(dutyPct);
  digitalWrite(CELL_PIN, HIGH);         // share the cell charge onto BL
  delayMicroseconds(30);
  digitalWrite(CELL_PIN, LOW);

  delayMicroseconds(t_dev_us);          // let the difference develop

  digitalWrite(FIRE_PIN, HIGH);         // power the latch - it decides now
  delayMicroseconds(200);

  int raw = analogRead(READ_PIN);
  digitalWrite(FIRE_PIN, LOW);
  return raw > (int)(ADC_MAX * 0.5f);   // did it land high?
}

void setup() {
  Serial.begin(115200);
  for (int p : {EQ_PIN, PRECHARGE_PIN, CELL_PIN, FIRE_PIN}) {
    pinMode(p, OUTPUT); digitalWrite(p, LOW);
  }
  analogSetPinAttenuation(READ_PIN, ADC_11db);
  ledcSetup(0, 20000, 8);
  ledcAttachPin(CELL_SET_PIN, 0);

  // ---- SWEEP 1: signal size, with a generous development time ----
  Serial.println("# sensitivity vs signal size (t_dev = 200 us)");
  Serial.println("duty_pct,trials,correct,error_rate");
  for (int duty = 2; duty <= 40; duty += 2) {
    int correct = 0;
    for (int i = 0; i < TRIALS; i++) if (senseOnce(duty, 200)) correct++;
    Serial.printf("%d,%d,%d,%.3f\n", duty, TRIALS, correct, 1.0f - (float)correct / TRIALS);
  }

  // ---- SWEEP 2: development time, at a signal that worked above ----
  Serial.println("# sensitivity vs development time (duty = 20%)");
  Serial.println("t_dev_us,trials,correct,error_rate");
  for (int t : {0, 1, 2, 5, 10, 20, 50, 100, 200, 500}) {
    int correct = 0;
    for (int i = 0; i < TRIALS; i++) if (senseOnce(20, t)) correct++;
    Serial.printf("%d,%d,%d,%.3f\n", t, TRIALS, correct, 1.0f - (float)correct / TRIALS);
  }

  Serial.println("# DONE - plot both sweeps in the jupyter step.");
  Serial.println("# Expect an S-curve, not a threshold. The width of the transition");
  Serial.println("# region IS your latch's offset and noise, measured rather than assumed.");
  Serial.println("# And note: at EVERY point above, the latch output is a clean full-swing");
  Serial.println("# logic level. It is never uncertain, only wrong.");
}

void loop() { }

Tools needed:

Desktop ComputerDesktop Computer
ESP32 Development BoardESP32 Development Board
Oscilloscope (2-Channel, 100MHz)Oscilloscope (2-Channel, 100MHz)
4

The signal budget — every millivolt accounted for

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Tools needed:

Desktop ComputerDesktop Computer
Notebook and PencilNotebook and Pencil

सामग्री

6

आवश्यक उपकरणहरू

6
Estimated Total
$20.00

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