The Chip-on-Board Breakout: From a 0.4 mm Mezzanine to Pins You Can Reach

From wafer.space's Run 1 documentation: the full-slot chip-on-board is 14 × 16 mm; the die's 74 bond pads follow the Tiny Tapeout convention, and all grounds are tied together on the default breakout. It carries a 70-pin, 0.4 mm pitch mezzanine connector (LCSC C19089236; the mating part is LCSC C19089262). So that every project fits the same boards, the default breakouts share the same wire-bonding layout, the same 14 × 16 mm footprint and the same connector position; traces, signal types and net assignments are left to the designer. wafer.space notes that pinouts, connectors and footprints are specific to each run.

Download the run-1/motherboards project from the repository and open it in KiCad. The files are saved by KiCad 10, so an older KiCad will not open them. Plot the Gerber and drill files and order the board from a PCB fabricator, with a solder-paste stencil for the mezzanine footprint. Hold the stencil over the mezzanine pads and spread lead-free solder paste across it in one stroke. Place the socket with fine tweezers, square to its pads, and reflow it with the hot-air station until the paste flows and settles. Inspect every one of the 70 joints with the loupe; clear any bridge between neighbouring pins with flux and the iron or hot air. Solder the two 1 × 35 pin headers with the iron. Before you plug in a chip, check with the multimeter that no two neighbouring header pins are shorted, and that each header pin reaches the socket pin the schematic connects it to.

**Sources**, read 29 September 2026: wafer.space's chip-on-board-wire-bonded-pcbs repository (README, run-1/README and run-1/motherboards, Apache-2.0). The schematic in step 4 is theirs, unchanged. The photograph is theirs too, from the same repository: a Run 1 chip-on-board seated on a Tiny Tapeout mezzanine adapter board (TTGF02, v0.1), not the header board built in step 5. **Honest limits.** This rung has not been built for this blueprint; the soldering steps are standard practice for a 0.4 mm surface-mount connector, not wafer.space instructions. The pinout and footprint are Run 1's, and wafer.space says they are expected to change in later runs, so check the current run's documentation before ordering boards.